1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a dual damascene structure.
2. Description of the Related Art
In the present semiconductor manufacturing process, copper has been widely used to make interconnection of integrated circuits due to its low resistance and its capability of preventing electromigration. Because it is not easy to etch copper, the metal dual damascene process has replaced the traditional process to manufacture copper lines.
As the semiconductor devices continue to be miniaturized, resistance-capacitance (RC) time delay among metal interconnection lines becomes an essential part for integrated circuits. For the present process, low dielectric constant materials and copper lines are used to enhance device performance. In addition, if the low dielectric constant porous material (with a dielectric constant lower than 2.2) is used, the RC time delay can be further prevented.
For the 0.18-μm semiconductor technology or other sub-micron technology, low dielectric constant materials have been widely used to reduce the RC time delay. Thermal stress, however, have great impact on low dielectric constant materials, especially for organic spin-on materials, such as silicon low-k (SILK™). On the other hand, since low dielectric constant materials formed by a chemical vapor deposition (CVD) method have better thermal conductivity than the materials formed by an organic spin-on method. Accordingly, how to integrate these two low dielectric constant materials to reduce the impact from thermal stress has become an important task in semiconductor manufacturing process.